On the performance advantage of PD/SOI CMOS with floating bodies

The performance advantage of floating-body (FB) partially depleted (PD) SOI CMOS technology is analyzed via device/circuit simulations, with emphasis on providing insight into the physical mechanisms underlying the advantage. Comparisons of predicted propagation delay of contemporary and scaled FB PD/SOI CMOS, including hysteresis, with those of the bulk-Si and body-tied-to-source/SOI counterparts, all with controlled off-state current, are made, and the impact of junction capacitance, the kink effect, and capacitive-coupling effects are quantified. Scaling the technologies is shown to diminish the performance advantage of FB PD/SOI CMOS, but this tendency can be mitigated by typically elevated operating temperatures, stacked-transistor logic, and device-design optimization