Properties of the transient of avalanche transistor switching at extreme current densities

Avalanche transistor switching at extreme currents is studied under conditions in which the charge of the excess carriers drastically rebuilds the collector field domain, causing fast switching and a low residual voltage across the switched-on device. The dynamic numerical model includes carrier diffusion and considers different dependencies of the velocities and ionization rates for the electrons and holes in the electric field. These dependences determine the principal difference in the switching process between n⁺-p-n₀-n⁺ and p⁺-n-p₀ -p⁺ structures. Reasonably good agreement is found between the simulated and measured temporal dependences of the collector current and voltage drop across the device for a particular type of avalanche transistor. Certain differences in the switching delay can partly be attributed to limitations in the one-dimensional (1-D) approach. It is now certain that collector domain reconstruction defines the transient in a n⁺-p-n₀-n⁺ transistor at high currents, but is not very pronounced in a p⁺ -n-p₀-p⁺ transistor. Some nontrivial features of the device operation are found, depending on the semiconductor structure. In particular, it is shown that the thickness of the low-doped collector region affects mainly the switching delay, and does not significantly effect the current rise time