Difference metric soft-output detection: architecture and implementation

Author

Gross, Warren J. ; Gaudet, Vincent C. ; Gulak, P. Glenn

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

48

Issue

10

fYear

2001

fDate

10/1/2001 12:00:00 AM

Firstpage

904

Lastpage

911

Abstract

The forward-backward (FB, also known as the MAP or BCJR) detection algorithm provides "soft" reliability estimates for each bit that it decodes. This paper presents a VLSI architecture for soft-output forward-backward detection of Class-IV partial response signaling (PR4) used in magnetic recording. A difference metric version of the FB algorithm is derived. A novel low-complexity architecture implements the computational kernel as a limiter. A 0.35-μm 3-level metal CMOS ASIC was implemented and verified to operate at 20 MHz (20 Mbps), the highest speed of our IC tester. Simulations predict operation of up to 150 Mbps

Keywords

AWGN channels; CMOS digital integrated circuits; VLSI; application specific integrated circuits; computational complexity; convolutional codes; digital magnetic recording; intersymbol interference; maximum likelihood decoding; maximum likelihood detection; partial response channels; trellis codes; 150 Mbit/s; 20 MHz; 20 Mbit/s; CMOS ASIC; Class-IV partial response signaling; MAP detection algorithm; PR4 signaling; VLSI architecture; additive white Gaussian noise channel; backward state metric recursion; computational kernel; convolutional decoding; decoding algorithm; difference metric soft-output detection; digital communication; forward state metric recursion; forward-backward detection algorithm; intersymbol interference; limiter; lookup table approach; low-complexity architecture; magnetic recording; sliding window architecture; soft reliability estimates; trellis stage; Application specific integrated circuits; CMOS integrated circuits; Computer architecture; Decoding; Detection algorithms; High speed integrated circuits; Kernel; Magnetic recording; Partial response signaling; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.974777

Filename

974777