Title :
Pseudo C-2C ladder-based data converter technique
Author_Institution :
Dept. of Electr. Eng., City Univ. of New York, NY, USA
fDate :
10/1/2001 12:00:00 AM
Abstract :
A C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of a C-2C ladder significantly deteriorate the linearity of the DAC and restrict its application. In this paper, a pseudo C-2C ladder structure is proposed. It maintains the advantages of conventional C-2C ladders and effectively compensates for the parasitic effects by adjusting the capacitor ratio a in a C-2αC ladder. As a result, high linearity may be achieved in standard CMOS technologies. The technique is illustrated with the design of a 12-bit CMOS DAC
Keywords :
CMOS integrated circuits; MOS capacitors; digital-analogue conversion; ladder networks; C-2αC ladder; C-2C ladder-based DAC; CMOS DAC; charge redistribution data conversion; differential nonlinearity; fast settling time; high linearity; integral nonlinearity; interconnecting nodes; parasitic capacitances; pseudo C-2C ladder structure; thermometer-code capacitor array; CMOS process; CMOS technology; Capacitors; Digital-analog conversion; Energy consumption; Impedance; Integrated circuit interconnections; Linearity; Parasitic capacitance; Semiconductor device modeling;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
