DocumentCode :
1558046
Title :
Efficient exponentiation using weakly dual basis
Author :
Wu, Huapeng ; Hasan, M. Anwar
Author_Institution :
Centre for Appl. Cryptographic Res., Waterloo Univ., Ont., Canada
Volume :
9
Issue :
6
fYear :
2001
Firstpage :
874
Lastpage :
879
Abstract :
A new architecture for finite field exponentiation using weakly dual bases is presented. An extended bidirectional linear feedback shift register is designed to multiply an arbitrary field element with certain essential multiplicands in weakly dual basis (WDB). Each of these multiplications is done in one single clock cycle. It is shown that a bit parallel implementation of the WDB fourth power has complexities comparable to those of polynomial basis fourth power. The proposed structure can effectively speed up the computation of exponentiation and is expected to reduce the power consumption compared to the conventional square and multiply scheme. Compared to the structure for polynomial basis exponentiation, the new structure is thus advantageous in a system where the WDB is already available.
Keywords :
computational complexity; logic design; logic testing; shift registers; clock cycle; extended bidirectional linear feedback shift register; finite field exponentiation; logic testing; weakly dual basis; Clocks; Computer architecture; Cryptography; Energy consumption; Error correction; Galois fields; Linear feedback shift registers; Polynomials; Shift registers; Table lookup;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.974900
Filename :
974900
Link To Document :
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