DocumentCode
1558063
Title
Multilevel reverse most-significant carry computation
Author
Bruguera, Javier D. ; Lang, Tomás
Author_Institution
Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain
Volume
9
Issue
6
fYear
2001
Firstpage
959
Lastpage
962
Abstract
A fast calculation of the most-significant carry in an addition is required in several applications. It has been proposed to calculate this carry by detecting the most-significant carry chain and collecting the carry after this chain. The detection can be implemented by a prefix tree of AND gates and the collecting by a multi-input OR. We propose a multilevel implementation, which allows the overlap of successive levels, thereby reducing the overall delay. For 64-bit operands we estimate a delay reduction of about 15% with respect to the traditional carry-lookahead-based method, with a similar hardware complexity.
Keywords
carry logic; computational complexity; logic design; trees (mathematics); AND gates; carry-lookahead-based method; computer arithmetic; hardware complexity; most-significant carry; multi-input OR; multilevel implementation; prefix tree; Arithmetic; Delay estimation; Fastbus; Hardware; Tree data structures; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.974909
Filename
974909
Link To Document