DocumentCode :
1559178
Title :
Production scheduling algorithms for a semiconductor test facility
Author :
Uzsoy, Reha ; Martin-Vega, Louis A. ; Lee, Chung-Yee ; Leonard, Paul A.
Author_Institution :
Sch. of Ind. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
4
Issue :
4
fYear :
1991
fDate :
11/1/1991 12:00:00 AM
Firstpage :
270
Lastpage :
280
Abstract :
The authors develop production scheduling algorithms for semiconductor test operations. The operations in the facility under study are characterized by a broad product mix, variable lot sizes and yields, long and variable setup times, and limited test equipment capacity. The approach presented starts by dividing the facility or job shop into a number of work centers. The method then proceeds to sequence one work center at a time. A disjunctive graph representation of the entire facility is used to capture interactions between work centers. The introduction of different management objectives leads to different work center problems and different production scheduling algorithms. The authors present algorithms for two different work center problems. Direction for future research are discussed
Keywords :
graph theory; integrated circuit testing; production testing; scheduling; semiconductor device testing; disjunctive graph representation; limited test equipment capacity; production scheduling algorithms; semiconductor test facility; variable lot sizes; variable setup times; variable yields; Automatic testing; Circuit testing; Job shop scheduling; Production; Scheduling algorithm; Semiconductor device testing; Software testing; Temperature; Test equipment; Test facilities;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.97809
Filename :
97809
Link To Document :
بازگشت