Title :
Use of screening and response surface experimental designs for development of a 0.5-μm CMOS self-aligned titanium silicide process
Author :
Jones, Robert E. ; Mele, Thomas C.
Author_Institution :
Motorola Inc., Austin, TX, USA
fDate :
11/1/1991 12:00:00 AM
Abstract :
A manufacturable self-aligned titanium silicide process for 0.5-μm CMOS technologies has been developed. Factorial and fractional-factorial screening experiments, as well as physical models, were used to identify important process factors. Central-composite and D-optimal response surface designs were used to optimize the process; short-loop process and device experiments and 0.5-μm technology static random access memory (SRAM) circuit flows were used. By using this comprehensive experimental design methodology, problems with diode leakage and silicide-to-silicon contact resistance were resolved, and specified device characteristics were achieved
Keywords :
CMOS integrated circuits; integrated circuit manufacture; metallisation; titanium compounds; 0.5 micron; CMOS; D-optimal type; SRAM; TiSi2-Si; central-composite type; design methodology; physical models; response surface experimental designs; screening; self-aligned process; short-loop process; static random access memory; submicron process; CMOS process; CMOS technology; Design for experiments; Design optimization; Manufacturing processes; Response surface methodology; Semiconductor device modeling; Silicides; Surface resistance; Titanium;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
