Use of screening and response surface experimental designs for development of a 0.5-μm CMOS self-aligned titanium silicide process

A manufacturable self-aligned titanium silicide process for 0.5-μm CMOS technologies has been developed. Factorial and fractional-factorial screening experiments, as well as physical models, were used to identify important process factors. Central-composite and D-optimal response surface designs were used to optimize the process; short-loop process and device experiments and 0.5-μm technology static random access memory (SRAM) circuit flows were used. By using this comprehensive experimental design methodology, problems with diode leakage and silicide-to-silicon contact resistance were resolved, and specified device characteristics were achieved