Efficient encoding of powers-of-two coefficients through minimum index floating point representation (MIFPR)

Reduction of hardware complexity of digital system has grown enormous interest amidst the researchers of late. As a matter of fact, a number of hardware efficient digital systems have been emerged in practice among which multiplier-less architecture is the most popular and effective one. Multiplier-less configuration restricts the tap-coefficients of any digital filter to assume values from a finite set encoded as sums and/ or differences of powers-of-two. In this paper, we have proposed a new scheme, called minimum index floating point representation (MIFPR), for the efficient design of multiplier-less filter. Comparative analysis of the proposed technique with some of the existing representation schemes related to power-of two filters has been presented and subsequently the best alternative has been suggested. Analytical results have also been substantiated by proper simulation results.