DocumentCode :
1559302
Title :
Design and analysis of even-sized binary shuffle-exchange networks for multiprocessors
Author :
Padmanabhan, Krishnan
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Volume :
2
Issue :
4
fYear :
1991
fDate :
10/1/1991 12:00:00 AM
Firstpage :
385
Lastpage :
397
Abstract :
The architecture and performance of binary shuffle-exchange networks of any size are investigated. It is established that a network with a shuffle-exchange stages whose number equals the least integer ⩾log2N or a single recirculating stage can provide the connectivity between N inputs and N outputs using a distributed tag-based control algorithm. Control tags depend on both source and destination when N is not a power of two and can be computed in a simple manner. Several structural and dynamic properties of the network are established, contrasting the behavior of the power-of-two and composite sized systems. The performance of the network in a stochastic environment is investigated analytically. It is shown that the shuffle-exchange networks behave in much the same way with respect to traffic and buffer capacity regardless of whether the system size is a power of two or not
Keywords :
multiprocessing systems; multiprocessor interconnection networks; parallel architectures; performance evaluation; architecture; binary shuffle-exchange networks; buffer capacity; connectivity; control tags; destination; distributed tag-based control algorithm; dynamic properties; multiprocessors; performance; source; stochastic environment; structural properties; traffic capacity; Concurrent computing; Distributed control; Helium; LAN interconnection; Multiprocessing systems; Performance analysis; Power system interconnection; Stochastic processes; Telecommunication traffic; Telephony;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/71.97896
Filename :
97896
Link To Document :
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