Title :
Reed-Solomon VLSI codec for advanced television
Author :
Whitaker, Sterling R. ; Canaris, John A. ; Cameron, Kelly B.
Author_Institution :
NASA Space Eng. Res. Center for VLSI Syst. Design, Idaho Univ., Moscow, ID, USA
fDate :
6/1/1991 12:00:00 AM
Abstract :
A VLSI implementation of a Reed-Solomon codec circuit is reported. The 1.6-μm double metal CMOS chip is 8.2 mm by 8.4 mm, contains 200000 transistors, operates at a sustained data rate of 80 Mbits/s and executes up to 1000 MOPS while consuming less than 500 mW of power. The 10-MHz sustained byte rate for the data is independent of the error pattern. The circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths of 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with selectable correction of up to ten symbol errors. Corrected data is output at a fixed latency. These features make this Reed-Solomon processor suitable for use in advanced television systems
Keywords :
CMOS integrated circuits; VLSI; codecs; digital signal processing chips; error correction codes; high definition television; 1.6 micron; 10 MHz; 1000 MFLOPS; 500 mW; 80 Mbit/s; ATV; HDTV; Reed-Solomon codec circuit; Reed-Solomon processor; VLSI; advanced TV systems; advanced television systems; block lengths; data rate; data/system clock; decoder; double metal CMOS chip; encoder; erasure corrections; random error corrections; shortened codes; symbol errors; transistors; Circuits; Clocks; Codecs; Decoding; Delay; Error correction; Reed-Solomon codes; TV; Transistors; Very large scale integration;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
