• DocumentCode
    1559502
  • Title

    Design method of a class of embedded combinational self-testing checkers for two-rail codes

  • Author

    Piestrak, Stainislaw J.

  • Author_Institution
    Inst. of Eng. Cybern., Tech. Univ. Wroclaw, Poland
  • Volume
    51
  • Issue
    2
  • fYear
    2002
  • fDate
    2/1/2002 12:00:00 AM
  • Firstpage
    229
  • Lastpage
    234
  • Abstract
    This paper tackles the open problem of designing combinational self-testing checkers (STCs) for K-pair 2-rail codes which are self-testing, even by a subset of codewords, such that some input lines are 0 (or 1) for only one input codeword. The checker presented in the paper has both theoretical and practical importance. It is useful, for example, to build STCs for other systematic error-detecting codes, like Berger codes with I = 2K-1 data bits and arithmetic codes with the check base A = 2K-1+I (K = 3, 4, 5, ...). It also allows the designers to build functional totally self-checking circuits with 100% fault coverage in which such 2-rail codes could not have been used otherwise
  • Keywords
    arithmetic codes; automatic testing; combinational circuits; embedded systems; error detection codes; network synthesis; Berger codes; arithmetic codes; check base; codeword subset; concurrent error detection; embedded circuit; embedded combinational self-testing checker design method; fault coverage; functional totally self-checking circuits; inverter-free circuit; self-testing 2-rail codes; systematic error-detecting codes; Built-in self-test; Design methodology;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.980010
  • Filename
    980010