• DocumentCode
    1559547
  • Title

    Modeling the economics of testing: a DFT perspective

  • Author

    Nag, Pranab K. ; Gattiker, Anne ; Wei, Sichao ; Blanton, R.D. ; Maly, Wojciech

  • Author_Institution
    Carnegie Mellon Univ., Pittsburgh, PA, USA
  • Volume
    19
  • Issue
    1
  • fYear
    2002
  • Firstpage
    29
  • Lastpage
    41
  • Abstract
    Decision-makers typically make test tradeoffs using models that mainly represent direct costs such as test generation time and tester use. Analyzing a test strategy´s impact on other significant factors such as test quality and yield learning requires an understanding of the dynamic nature of the interdomain dependencies of test, manufacturing, and design. Our research centers on modeling the tradeoffs between these domains. To answer the DFT question, we developed the Carnegie Mellon University Test Cost Model, a DFT cost-benefit model, derived inputs to the model for various IC cases with different assumptions about volume, yield, chip size, test attributes, and so forth; and studied DFT´s impact on these cases. We used the model to determine the domains for which DFT is beneficial and for which DFT should not be used. The model is a composite of simple cause-and-effect relationships derived from published research. It incorporates many factors affecting test cost, but we don´t consider it a complete model. Our purpose is to illustrate the necessity of using such models in assessing the effectiveness of various test strategies
  • Keywords
    cost-benefit analysis; design for testability; integrated circuit economics; integrated circuit testing; Carnegie Mellon University Test Cost Model; DFT; DFT cost-benefit model; IC testing; cause-and-effect relationships; test quality; test yield; testing economics modeling; Cost function; Design for testability; Integrated circuit modeling; Integrated circuit testing; Life testing; Personnel; Semiconductor device modeling; Silicon; Software testing; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.980051
  • Filename
    980051