Title :
Thorough testing of any multiport memory with linear tests
Author :
Hamdioui, Said ; Van de Goor, Ad J.
Author_Institution :
Lab. of Comput. Eng., Delft Univ. of Technol., Netherlands
fDate :
2/1/2002 12:00:00 AM
Abstract :
The quality of tests, in terms of fault coverage and test length, is strongly dependent on the used fault models. This paper presents realistic fault models for multiport memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ..., p-port faults. In addition, the paper discusses the test procedure for such memories; it shows that the time complexity of the required tests is not exponential proportionally with p, as published by different authors, but it is linear, irrespective of the number of ports of which the multiport memory consists
Keywords :
SPICE; circuit complexity; fault simulation; integrated circuit testing; integrated memory circuits; multiport networks; random-access storage; SPICE simulation; bridges; defect injection; fault coverage; fault models; fault probabilities; functional models; linear tests; memory cell array; multiport memory; opens; optimal tests; p ports; realistic models; shorts; single-port faults; spot defects; test length; thorough testing; time complexity; two-port faults; weak faults; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Costs; Interference; Read-write memory; SPICE;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
