Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
Abstract :
Very large scale integration (VLSI) fabrication technology has advanced rapidly, bringing with it a strong demand for faster and better design automation tools. Accurate reporting of results for placement approaches is crucial to the development of improved automation tools; unfortunately, publicly available placement benchmarks are outdated, and there are wide variations in their interpretation. In addition, the metrics considered by some academic research have questionable relevance to modern design. At best, poor benchmarks and differences in interpretation result in misunderstandings of the effectiveness of some approaches. At worst, they can motivate research in areas of very little promise, while other areas which have true potential are ignored. In this paper, we expand on work previously presented, describing current standard cell placement benchmarks and illustrating common differences in their interpretation. We also propose specific interpretation methods for traditional objectives, and discuss new metrics which should be considered in modern placement research. Our hope is that by presenting these issues clearly, we can enable more accurate evaluations of placement methods, and improve research efficiency
Keywords :
VLSI; cellular arrays; circuit layout CAD; logic CAD; logic partitioning; minimisation of switching nets; MCNC suite; VLSI; area minimization; benchmarks; computer-aided design; design automation; hypergraph partitioning; interpretation methods; reporting of results; routability; standard cell design; standard cell placement; wire length; Circuits; Delay; Design automation; Design optimization; Fabrication; Large scale integration; Minimization; Partitioning algorithms; Very large scale integration; Wire;