Title :
40-Gb/s all-optical packet synchronization and address comparison for OTDM networks
Author :
Hamilton, S.A. ; Robinson, B.S.
Author_Institution :
Lincoln Lab., MIT, Lexington, MA, USA
Abstract :
We demonstrate a novel optical time division multiplexing packet-level system-synchronization and address-comparison technique, which relies on cascaded semiconductor-based optical logic gates operating at 50-Gb/s line rates. Synchronous global clock distribution is used to achieve fixed length packet-synchronization that is resistant to channel-induced timing delays, and straightforward to achieve using a single optical logic gate. Four-bit address processing is achieved using a pulse-position modulated header input to a single optical logic gate, which provides Boolean XOR functionality, low latency, and stability over >1 h time periods with low switching energy <100 fJ.
Keywords :
Boolean functions; clocks; logic gates; optical communication equipment; optical fibre networks; optical logic; optical modulation; optical switches; packet switching; pulse position modulation; synchronisation; time division multiplexing; timing; 1 hr; 100 fJ; 40 Gbit/s; 50 Gbit/s; Boolean XOR functionality; Four-bit address processing; OTDM networks; OTDM packet-level system-synchronization/address-comparison technique; address processing; all-optical address comparison; all-optical packet synchronization; cascaded semiconductor-based optical logic gates; channel-induced timing delays; fixed length packet-synchronization; latency; operating line rates; optical logic gate; optical time division multiplexing; pulse-position modulated header input; stability; switching energy; synchronous global clock distribution; time periods; ultrafast nonlinear interferometer; Clocks; Delay; Logic gates; Optical modulation; Optical pulses; Pulse modulation; Stability; Synchronization; Time division multiplexing; Timing;
Journal_Title :
Photonics Technology Letters, IEEE
