Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this performance/costs challenge is given by customizable multiprocessor system-on-chips. The approach proposed in this paper leads to the customization of multi/many processor system-on-chip at two levels of abstraction: 1) customization through application-specific hardware accelerators implemented on configurable datapath that can target three kinds of structured application-specific integrated circuit technologies: metal, via, and runtime programmable and 2) customization of the architectural parameters of the platform. The proposed platform is equipped with a design framework that assists the user in the high-level design-space exploration of signal processing applications described using the Open Computing Language (OpenCL) language. A peculiar added value of the flow is to support the migration of OpenCL kernels and tasks into pipelined hardware accelerators described using a C-level language. The platform is able to provide an average performance of 90 GOPS on a set of reference signal processing applications, and an average computational energy efficiency of 130 GOPS/W in its metal-programmable configuration. This result shows the benefits in terms of energy efficiency of hardware customization applied to multiprocessor systems with respect to many core devices such as general-purpose graphic processing units, able to provide on average 2.5 GOPS/W for the applications under analysis.