DocumentCode :
1559840
Title :
Ferroelectric DRAM (FEDRAM) FET with metal/SrBi2Ta2O/sub 9//SiN/Si gate structure
Author :
Kwang-Ho Kim ; Jin-Ping Han ; Soon-Won Jung ; Tso-Ping Ma
Author_Institution :
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Volume :
23
Issue :
2
fYear :
2002
Firstpage :
82
Lastpage :
84
Abstract :
N-channel ferroelectric dynamic random access memory (FEDRAM) FETs with SrBi2Ta2O/sub 9//SiN/Si structure were fabricated and characterized. The estimated switching time (t/sub sw/) of the fabricated FET, measured at applied electric field of 376 kV/cm, was less than 50 ns, which could be significantly reduced upon scaling. Its remnant polarization (2P/sub r/) was measured to be about 1.5 μC/cm2, which is more than one order of magnitude higher than that required for FEDRAM operation. The stored information retains more than three orders of magnitude of on/off ratio up to three days at room temperature, with little fatigue after 10/sup 11/ switching cycles.
Keywords :
DRAM chips; MISFET; bismuth compounds; ferroelectric storage; silicon; silicon compounds; strontium compounds; 50 ns; FEDRAM FET; N-channel ferroelectric dynamic random access memory; SrBi/sub 2/Ta/sub 2/O/sub 9/-SiN-Si; device scaling; fatigue; metal/SrBi/sub 2/Ta/sub 2/O/sub 9//SiN/Si gate structure; on/off ratio; remnant polarization; switching time; DRAM chips; Electric variables measurement; FETs; Fatigue; Ferroelectric materials; Polarization; Random access memory; Silicon compounds; Temperature; Time measurement;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.981313
Filename :
981313
Link To Document :
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