Title :
Word-parallel CRC computation on VLIW DSP
Author :
Hubaux, D. ; Legat, J.-D.
Author_Institution :
Microelectron. Lab., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium
fDate :
1/17/2002 12:00:00 AM
Abstract :
Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances, a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using the full power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method is at least four times faster for 8, 16 and 32 bits CRC
Keywords :
digital signal processing chips; error detection; parallel algorithms; parallel architectures; redundancy; 16 bit; 32 bit; 8 bit; CRC computation; VLIW DSP; VLIW DSP architecture; bit-parallel processing; cyclic redundancy check; error detection; optimal performance; parallel processor architecture; very long instruction word digital signal processor; word-parallel CRC computation; word-parallel algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020047
