Impact of substrate thickness on single-event effects in integrated circuits

Author

Dodd, P.E. ; Shaneyfelt, M.R. ; Fuller, E. ; Pickel, J.C. ; Sexton, F.W. ; Winokur, P.S.

Author_Institution

Sandia Nat. Labs., Albuquerque, NM, USA

Volume

48

Issue

6

fYear

2001

fDate

12/1/2001 12:00:00 AM

Firstpage

1865

Lastpage

1871

Abstract

The effects of substrate and epitaxial-layer thickness on the single-event upset and single-event latchup response of integrated circuits are studied using experiments and three-dimensional device simulations. Reducing substrate thickness can be an effective method for improving single-event upset and latchup immunity, but only if devices are thinned beyond their epitaxial-layer thickness. Increases in overall single-event upset threshold linear energy transfer of more than a factor of two are predicted after thinning to a wafer thickness of 0.5 μm. Simulations predict that the single-event latchup performance of a thinned integrated circuit will be similar to that of the same integrated circuit fabricated on an epitaxial substrate of equivalent thickness. By combining wafer thinning with backside contact formation, more significant improvements in the single-event latchup threshold can be obtained

Keywords

circuit simulation; integrated circuit modelling; radiation effects; semiconductor epitaxial layers; space vehicle electronics; 0.5 micron; backside contact formation; epitaxial-layer thickness; equivalent thickness; single-event effects; substrate thickness; three-dimensional device simulations; threshold linear energy transfer; wafer thickness; CMOS technology; Circuit simulation; Energy exchange; Helium; Manufacturing; Orbits; Predictive models; Resistors; Single event upset; Substrates;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.983144

Filename

983144