Impact of substrate thickness on single-event effects in integrated circuits

The effects of substrate and epitaxial-layer thickness on the single-event upset and single-event latchup response of integrated circuits are studied using experiments and three-dimensional device simulations. Reducing substrate thickness can be an effective method for improving single-event upset and latchup immunity, but only if devices are thinned beyond their epitaxial-layer thickness. Increases in overall single-event upset threshold linear energy transfer of more than a factor of two are predicted after thinning to a wafer thickness of 0.5 μm. Simulations predict that the single-event latchup performance of a thinned integrated circuit will be similar to that of the same integrated circuit fabricated on an epitaxial substrate of equivalent thickness. By combining wafer thinning with backside contact formation, more significant improvements in the single-event latchup threshold can be obtained