Title :
Exploiting circuit emulation for fast hardness evaluation
Author :
Civera, P. ; Macchiarulo, L. ; Rebaudengo, M. ; Reorda, M. Sonza ; Violante, M.
Author_Institution :
Dipt. di Elettronica, Politecnico di Torino, Italy
fDate :
12/1/2001 12:00:00 AM
Abstract :
Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit emulation for performing fault-injection campaigns. Experimental results show that the new technique is about four orders of magnitude faster than simulation-based fault injection
Keywords :
VLSI; failure analysis; field programmable gate arrays; integrated circuit reliability; integrated circuit testing; radiation hardening (electronics); circuit emulation; fast hardness evaluation; fault-injection; field-programmable gate-array based circuit emulation; hardening mechanisms; safety-critical VLSI circuits; simulation-based fault injection; Circuit faults; Circuit simulation; Circuit testing; Emulation; Error analysis; Field programmable gate arrays; Helium; Instruments; Single event upset; Very large scale integration;
Journal_Title :
Nuclear Science, IEEE Transactions on
