Title :
A hardware-like high-level language based environment for 3D graphics architecture exploration
Author :
Lee, Inho ; Kim, Joung-Youn ; Im, Yeon-Ho ; Choi, Yunseok ; Shin, Hyunchul ; Han, Clmngyoung ; Kim, Donghyun ; Park, Hyoungjoon ; Seo, Young-11 ; Chung, Kyusik ; Yu, Chang-Hyo ; Chun, Kanghyup ; Lee-Sup Kim
Author_Institution :
Multimedia VLSI Lab., KAIST, Daejeon, South Korea
Abstract :
The high complexity and the short lifetime of 3D graphics acceleration hardware increase the necessity of an environment for hardware development. For easy modification and fast testing of architecture, a high-level language based environment is desirable. Therefore, in this paper we propose a Graphics Architecture Testing Environment (GATE) that is based on Microsoft Visual C++. GATE models overall graphics hardware architecture through a modular approach, supports OpenGL, and offers easy modification and rapid testing of architecture. It also gathers computational statistics. A layered approach and Hardware Description Macro (HDM) support hardware modeling and architecture modification. Pre-defined types and operations provide statistical information. Several case studies of 3D graphics architecture on GATE show the capability of our environment.
Keywords :
C++ language; computer graphics; development systems; visual languages; 3D graphics architecture exploration; Graphics Architecture Testing Environment; Hardware Description Macro; Microsoft Visual C++; OpenGL; computational statistics; graphics acceleration hardware; hardware development; hardware-like high-level language based environment; layered approach; statistical information; Acceleration; Computer architecture; Debugging; Engines; Graphics; Hardware; High level languages; Pipeline processing; Power system modeling; Testing;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206023