Title :
High speed memory efficient EBCOT architecture for JPEG2000
Author :
Fang, Hung-Chi ; Wang, Tu-Chih ; Lian, Chung-Jr ; Chang, Te-Hao ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a high speed, memory efficient architecture of embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000. By parallel coding all the bitplanes, the state variable memory can be eliminated. The proposed architecture can process 50 M coefficients per second at 100 MHz, which can realtime encode 720p resolution of HDTV picture format at 30 fps.
Keywords :
CMOS digital integrated circuits; code standards; data compression; digital signal processing chips; entropy codes; high definition television; high-speed integrated circuits; image coding; parallel architectures; 100 MHz; HDTV picture format; JPEG2000 standard; bitplane coding; embedded block coding; entropy coding algorithm; high speed architecture; memory efficient EBCOT architecture; memory-saving parallel architecture; optimized truncation; parallel coding; state variable memory; still image coding; Block codes; Design engineering; Design optimization; Digital signal processing; Discrete wavelet transforms; Energy consumption; High speed integrated circuits; Image storage; Memory architecture; Transform coding;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206079
