Supersystolic arrays on large-scale FPGA structures

A system-on-a-chip with reconfigurable hardware such as SRAM-based FPGAs is evidently suitable for several applications on wearable computers. However, interconnect delay of current state-of-the-art FPGAs dominates the logic delay with relatively high power consumption. To counterbalance these two problems while maintaining desirable performance, voltage downscaling and fine-grained pipelining have been suggested. In this paper, we propose a pipelining methodology to utilize intra-iteration parallelism of a systolic-like array realized in a multi million-gate FPGA. This results in not only enhanced throughput but also much higher hardware utilization. Thus, we call it the supersystolic array.