A high-efficiency reconfigurable digital signal processor for multimedia computing

In this work, a high-efficiency reconfigurable digital signal processor (DSP) that consists of two arithmetic logic units and a reconfigurable computation unit is designed. The design methodology for the reconfigurable computation unit is explored based on the intermediate grain framework. The proposed reconfigurable computation unit includes 8/spl times/8 array processing elements and interconnection paths where the processing element is based on two 8-bit ripple adders and simple logic gates. This reconfigurable computation unit can be configured to perform special operations such as two 16/spl times/16-bit multiplication, sixteen 32-bit addition/subtraction, one 16-bit dot product and sixteen 8-bit absolute that utilize these 64 processing elements in different connection topologies to increase their usage rates. In the benchmark analyses, the 8/spl times/8-pixel motion estimation and 8/spl times/8-pixel discrete cosine transform are realized in the proposed reconfigurable DSP, TI TMS320C64 and MorphoSys. Additionally, the comparison of computation performances and hardware costs is performed to show that the proposed reconfigurable DSP is able to achieve a higher computation performance at a low hardware cost. Therefore, the reconfigurable DSP proposed herein can achieve high-efficiency computing for various multimedia applications.