Parallel 4×4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264

Author

Wang, Tu-Chih ; Huang, Yu-Wen ; Fang, Hung-Chi ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

2

fYear

2003

Abstract

Transform coding has been widely used in video coding standards. In this paper, a hardware architecture for accelerating transform coding operations in MPEG-4 AVC/H.264 is presented. This architecture calculates 4 inputs in parallel by fast algorithms described previously. The transpose operations are implemented by a register array with directional transfers. This architecture has been mapped into a 4 × 4 multiple transforms unit and synthesized in TSMC 0.35um technology. The multiple transform processor can process 320M pixels/sec at 80Mhz for all 4 × 4 transforms used in MPEG-4 AVC/ H.264.

Keywords

digital signal processing chips; parallel architectures; telecommunication standards; transform coding; video coding; 0.35 micron; 2D inverse transform; 2D transform; 80 MHz; MPEG-4 AVC/H.264 standard; hardware architecture; multiple transform processor; parallel architecture; register array; transform coding; video coding; Automatic voltage control; Codecs; Design engineering; Digital signal processing; Discrete cosine transforms; Encoding; Hardware; MPEG 4 Standard; Transform coding; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206095

Filename

1206095