Title :
Test structures for the characterisation of MEMS and CMOS integration technology
Author :
Lin, H. ; Walton, A.J. ; Dunarc, C.C. ; Stevenson, J.T.M. ; Gundlach, A.M. ; Smith, S. ; Bunting, A.S.
Author_Institution :
Sch. of Eng. & Electron., Edinburgh Univ., UK
Abstract :
Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7-9 Ω resistances for via chain structures. Via contact resistances of 6 × 10-8 Ω·cm2 were measured using Kelvin test structures.
Keywords :
CMOS integrated circuits; chemical mechanical polishing; contact resistance; integrated circuit interconnections; micromechanical devices; wafer bonding; wafer-scale integration; 7 to 9 ohm; CMOS wafers; CMP planarisation; Kelvin test structures; chemical mechanical polishing; electrical connections; integrated system; low temperature bonding; microelectromechanical systems; wafer interconnects; wafer thinning; CMOS technology; Contacts; Electrical resistance measurement; Kelvin; Micromechanical devices; Planarization; Process design; System testing; Temperature; Wafer bonding;
Conference_Titel :
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on
Print_ISBN :
1-4244-0167-4
DOI :
10.1109/ICMTS.2006.1614292
