DocumentCode :
1560910
Title :
Novel test structures for on-chip characterization of coupling capacitance variation by in- and anti-phase crosstalk in multi-level metallization
Author :
Lee, Hi-Deok ; Ji, Hee-Hwan ; Han, In-Sik ; Joo, Han-Soo ; Kim, Dae-Mann ; Park, Sung-Hyung ; Lee, Heui-Seung ; Ho, Won-Joon ; Kim, Dae-Byung ; Cho, Ihl-Hyun ; Kim, Sang-Young ; Hwang, Sung-Bo ; Lee, Jeong-Gon ; Park, Jin-Won
Author_Institution :
Dept. of Elec. Eng., Chungnam Nat. Univ., Daejeon, South Korea
fYear :
2006
Firstpage :
218
Lastpage :
221
Abstract :
Novel test structure is proposed for on-chip evaluation of the crosstalk-induced variation of coupling capacitance in multi-fanout and global interconnect lines. Then, it is experimentally shown that the crosstalk-induced variation of coupling capacitance, ΔCC can be larger than the static coupling capacitance, CC for both multi-fanout and global interconnect using the novel on-chip test structures. HSPICE simulation is performed to confirm the experimental data.
Keywords :
capacitance; crosstalk; integrated circuit interconnections; integrated circuit metallisation; HSPICE simulation; antiphase crosstalk; coupling capacitance variation; crosstalk-induced variation; global interconnect lines; inphase crosstalk; multi-level metallization; multifanout interconnect lines; on-chip characterization; static coupling capacitance; test structures; Capacitance; Coupling circuits; Crosstalk; Delay effects; Integrated circuit interconnections; Metallization; Ring oscillators; Testing; Time measurement; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on
Print_ISBN :
1-4244-0167-4
Type :
conf
DOI :
10.1109/ICMTS.2006.1614307
Filename :
1614307
Link To Document :
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