DocumentCode :
1561104
Title :
IO latency hiding in pipelined architectures
Author :
Siewert, Sam
Author_Institution :
Colorado Univ., Boulder, CO, USA
fYear :
2005
Firstpage :
39
Lastpage :
45
Abstract :
This paper reports upon development of a novel mathematical formalism for analyzing data pipelines. The method accounts for IO and CPU latencies in the stages of the data pipeline. An experimental pipeline was constructed using a video encoder, frame processing, and transport of the frames over an IP (Internet protocol) network. The pipelined architecture provides a method to overlap processing with DMA, encoding and network transport latency so that streams can be processed with optimal scalability. The model expectations were compared with experimental test results and found to be consistent. The model is therefore expected to provide a good estimate for the scalability of streaming video-on-demand systems. Video-on-demand is a rapidly growing service segment for entertainment, advertising, on-line education, and a myriad of emergent applications.
Keywords :
data communication; mathematical analysis; pipeline processing; transport protocols; video coding; video communication; video on demand; CPU latency; DMA latency; IO latency hiding; Internet protocol network; data pipeline analysis; encoding latency; frame processing; frame transport; mathematical formalism; network transport latency; pipelined architectures; video encoder; video-on-demand systems; Advertising; Data analysis; Delay; Encoding; IP networks; Pipelines; Scalability; Streaming media; Testing; Transport protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Technical, Professional and Student Development Workshop, 2005 IEEE Region 5 and IEEE Denver Section
Print_ISBN :
0-7803-8898-4
Type :
conf
DOI :
10.1109/TPSD.2005.1614345
Filename :
1614345
Link To Document :
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