Design and development of stacked die technology solutions for memory packages

With the demand in increased functionality for consumer electronics and the need for form factor reduction, stacked die packages have gained its popularity over the recent years. The most efficient way to increase a memory package´s capacity without increasing its size is to adopt a die stacking structure. This paper presents three innovative package technologies for DRAM memory packages, with the option of die stacking structures of D2i/D2-wCSP (window chip scale package), D2-FBGA and 2DD2-wCSP. Upfront design considerations such as package structure, electrical performance and board level reliability are discussed. Customised assembly processes are developed for each package type, with full package level reliability qualification. Each package design demonstrated its unique advantages and careful selection of a packaging solution is necessary in meeting individual customer´s specific requirements