DocumentCode :
1561255
Title :
SPA - a synthesisable Amulet core for smartcard applications
Author :
Plana, L.A. ; Riocreux, P.A. ; Bainbridge, W.J. ; Bardsley, A. ; Garside, J.D. ; Temple, S.
Author_Institution :
Dept. of Comput. Sci., Manchester Univ., UK
fYear :
2002
Firstpage :
201
Lastpage :
210
Abstract :
SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective, albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed to evaluate the applicability of self-timed logic in security-sensitive devices. The Balsa synthesis system is used to generate dual-rail logic with some enhancements to improve security against non-invasive attacks. A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system.
Keywords :
application specific integrated circuits; integrated circuit interconnections; microprocessor chips; smart cards; ARM-compatible processor core; Balsa synthesis system; SPA; area; dual-rail logic; noninvasive attacks; on-chip interconnection system; performance; rapid implementation; security-sensitive devices; self-timed logic; self-timed processor core; synthesisable Amulet core; system-on-chip; Application software; Central Processing Unit; Circuit testing; Computer science; Electromagnetic analysis; Integrated circuit interconnections; Logic devices; Security; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on
ISSN :
1522-8681
Print_ISBN :
0-7695-1540-1
Type :
conf
DOI :
10.1109/ASYNC.2002.1000310
Filename :
1000310
Link To Document :
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