Variable delay ripple carry adder with carry chain interrupt detection

Author

Burg, Andreas ; Girkaynak, F.K. ; Kaeslin, Hubert ; Fichtner, Wolfgang

Author_Institution

Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland

Volume

5

fYear

2003

Abstract

A statistical approach for the area efficient implementation of fast wide operand adders using early termination detection is described and analyzed. It is shown that high throughput can be achieved based on area- and routing-efficient ripple-carry adders with only marginal overhead. They share a low AT-product with Brent-Kung adders but provide designers with totally different area/delay tradeoffs. The circuit does not require full-custom design and fits well into both self-timed and synchronous designs.

Keywords

adders; carry logic; circuit optimisation; delay estimation; integrated circuit design; integrated logic circuits; logic design; timing; area efficient implementation; area-efficient adders; area/delay tradeoffs; carry chain interrupt detection; early termination detection; fast wide operand adders; high throughput; low AT-product; routing-efficient adders; self-timed designs; statistical approach; synchronous designs; variable delay ripple carry adder; Added delay; Adders; Circuits; Clocks; Design methodology; Laboratories; Performance analysis; Throughput; Timing; Zirconium;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206202

Filename

1206202