Optimal use of 2-phase transparent latches in buffered maze routing

Clocking frequencies continue to increase due to the demand for higher performance. Together with the larger die sizes, multiple clock cycles are now required to cross a chip. A routing tool must thus insert registers as well as buffers while minimizing the path latency. This paper addresses optimal buffered path construction across multiple clock cycles using 2-phase transparent latches. We demonstrate the benefits of routing using latches over registers, and we present a polynomial routing algorithm. Our results confirm the correctness of our algorithm.