Design of a self-timed asynchronous parallel FIR filter using CSCD

This paper presents a self-timed, asynchronous, parallel finite impulse response (FIR) filter architecture capable of high-speed operation. Using self-timed, parallel structures even slow calculation blocks, such as simple multiplier-accumulators (MACs), can be used to implement high-speed filters. The building blocks are implemented using specific current-sensing completion detection (CSCD) standard cells also presented in this paper. The simulation results are very promising and especially the design of the control revealed several pitfalls and possibilities that require specific solutions when designing asynchronous circuits.