DocumentCode
1561735
Title
Novel recharge semi-floating-gate CMOS logic for multiple-valued systems
Author
Berg, Y. ; Aunet, S. ; Minnotahari, O. ; Hovin, M.
Author_Institution
Dept. of Inf., Oslo Univ., Norway
Volume
5
fYear
2003
Abstract
In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.
Keywords
CMOS logic circuits; low-power electronics; multivalued logic circuits; dynamic power dissipation; low-power digital circuit; mixed-mode design; multiple-valued system; power dissipation; recharge semi-floating-gate CMOS logic circuit; CMOS logic circuits; Clocks; Digital circuits; Digital systems; Inverters; Logic circuits; Logic design; Logic gates; Logic programming; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206229
Filename
1206229
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