Title :
Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference
Abstract :
The following topics are dealt with: architecture-specific synthesis; partitioning and clustering; high-level synthesis; placement; circuit and multilevel simulation; routing; formal verification and fault tolerances; hardware/software codesign; heterogeneous system level specification and design; module generation; timing analysis and delay faults; design for testability; scheduling and allocation; test pattern generation and diagnosis; concurrent engineering; FPGA (field programmable gate array) synthesis; framework components; Boolean matching and spectral methods; framework implementations; logic synthesis; user view of testing and timing; VHDL (VHSIC (very high-speed integrated circuit) hardware description language) and testing; modeling with VHDL; design techniques in VHDL; formal methods; specification and simulation; and VHDL and synthesis
Keywords :
Boolean functions; VLSI; automatic testing; circuit CAD; circuit reliability; concurrent engineering; delays; design for testability; digital simulation; field programmable gate arrays; formal logic; formal verification; hardware description languages; high level synthesis; integrated circuit design; integrated circuit testing; logic CAD; logic design; logic partitioning; pattern classification; programmable logic arrays; scheduling; very high speed integrated circuits; architecture-specific synthesis; clustering; high-level synthesis; multilevel si; partitioning; placement;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg, Germany
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410605
