Title :
Area efficient, high speed parallel counter circuits using charge recycling threshold logic
Author :
Celinski, Peter ; Abbott, Derek ; Cotofana, Sorin D.
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Abstract :
The main result is the development of a low depth, highly compact implementation of parallel counters (i.e., population counters), based on threshold logic. Two such counters are designed using the recently proposed Charge Recycling Threshold Logic (CRTL) gate. The novel feature of the designs is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 35% in the required number of capacitors for the (7,3) counter and by over 60% for the (15,4) counter. This reduces the total area by approximately 37% for the (7,3) counter and by 60% for the (15,4) counter, with no increase in delay. The proposed (7,3) counter design is also shown to be 45% faster compared to a conventional Boolean full-adder based circuit.
Keywords :
CMOS logic circuits; counting circuits; logic design; logic gates; parallel processing; threshold logic; CRTL gate; area efficient counter circuits; capacitive network; charge recycling threshold logic; high speed parallel counter circuits; highly compact implementation; population counters; weighted sum; Boolean functions; CMOS logic circuits; Counting circuits; Input variables; Integrated circuit technology; Logic circuits; Logic design; Logic gates; Recycling; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206239
