Reliability of Cu/low-k wafer level package (WLP)

With the move to 300 mm wafer, WLP becomes even more attractive as the solution for backend processing. More importantly as an enabling technology for the most advanced 0.13 micron technology using Cu/low-k interconnect devices. Cu/low-k devices need WLP since wire-bond forces could damage the soft device structures. Additionally, low-k interconnect densities often reach values that can only be accommodated by area-array packaging technology. Low-k materials are mechanically, chemically, thermally, and electrically less stable than the historical material of choice, SiO₂. Therefore, the challenge lies not only in identifying and characterizing the candidate materials, but also in devising the best method to integrate those materials for packaging. Test wafer was fabricated with 4 Cu/low-k (black diamond) dielectrics layers. And it has multilayer via-chain to check the internal ILD stack reliability. Die size was 15mm times 15mm and IO no. was about 800. Using these test wafers, WLP was fabricated with multidielectrics layers (BCB) and Cu metal redistribution. Wafer level package has 300 mum pitch solder bump and Cu post interconnects to get better board level solder joint reliability. Cu post and solder cap were prepared by electroplating method. To investigate the solder joint integrity, daisy chains are connected to the PCB board and resistance was electrically monitored. Board level solder joint reliability is performed in temperature cycle chamber (-45/120C)