The design and implementation of multidimensional systolic arrays for DSP applications

The authors present a technique for transforming DSP (digital signal processing) algorithms to a form suitable for multidimensional systolic array implementation. The aim of the transformation is to speed up computation without much increase in area requirement. The price to be paid is the small amount of additional circuitry (usually in the form of adders and interconnection wires) required for interrow or interplane communications. The application of the technique to some DSP algorithms is presented. The systolic networks produced are implemented using NORA CMOS logic structure and laid out using 3-μm CMOS p-well technology. Areas and times for the resulting architectures are evaluated and discussed