Regular schedules for scalable design of IIR filters

The authors present regular schedules, a class of parallel schedules for computing mth-order infinite-impulse response (IIR) filters. These schedules permit the implementation of IIR filters on a family of scalable parallel architectures with varying price/performance characteristics, enabling designers to effectively explore the design space of parallel IIR filter implementations. The technique is illustrated on a target architecture comprising application-specific instruction processors (ASIPs) clustered on multichip modules (MCMs), with the MCMs connected through a scalable interconnection network. The simplicity of the regular schedules facilitates characterization of their interprocessor communications, which makes it possible to generate instruction-level behavior of the design that can be easily mapped onto ASIP architectures. Preliminary results of design space exploration for the fifth-order elliptic wave filter benchmark on the interconnected ASIP architectures are presented