Design of a 32-bit squarer - exploiting addition redundancy

In this paper, a new architecture for signed and unsigned binary number squarer is given. The method is applied to the design of a 32-bit squarer using Wallace-tree and carry select adder. The proposed design is analytically compared with the conventional designs. For quantitative analysis, the squarer and general-purpose multipliers are synthesized in FPGA using Xilinx 4052x1-1 FPGA technology. The experimental results demonstrate the effectiveness of the proposed method in terms of delay, power and area reduction.