Voltage scaling and repeater insertion for high-throughput low-power interconnects

Due to exponential increases in both the number of transistors per chip and clock frequency, the dynamic power dissipation for high performance microprocessors is increasing rapidly. This paper, therefore, explores opportunities to reduce global interconnect power dissipation through optimal supply voltage scaling and repeater insertion. To this end, the throughput-energy product and throughput per bit-energy are analyzed to determine an optimum supply voltage for a typical global interconnect in 180 nm technology. Case studies illustrate that a 1 V supply voltage can reduce the power to almost 25% of that using a 2.5 V supply, without any loss in throughput performance (e.g. 2 Gbps) or increase in the wire area.