Title :
A triple port RAM based low power commutator architecture for a pipelined FFT processor
Author :
Hasan, Mohd ; Arslan, Tughrul
Author_Institution :
Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK
Abstract :
This paper proposes a low power commutator architecture based on triple port RAMs rather than dual port RAMs or conventional FIFO for the radix-4 pipelined FFT processor implementation. The triple port RAM based commutator consumes less power than the other two for the first and second stages of a 64-point radix-4 pipelined FFT processor. This commutator is attractive for shorter FFTs but can also be used in the last stages of longer FFTs. Up to 29% and 9% power savings is achieved for the 8-12 bit data range in the second and first stages of a 64-point FFT processor respectively.
Keywords :
circuit simulation; digital signal processing chips; fast Fourier transforms; logic design; logic simulation; low-power electronics; pipeline arithmetic; random-access storage; 8 to 12 bit; data range bit size; low power commutator architecture; pipelined FFT processor; power savings; radix-4 pipelined FFT; triple port RAM; triple port RAM based FFT processor; CMOS logic circuits; Clocks; Digital signal processing chips; Discrete Fourier transforms; Energy consumption; Equations; Multiplexing; Portable computers; Shift registers; Throughput;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206278
