DSP engine for ultra-low-power audio applications [codec application]

Author

Morling, R.C.S. ; Kale, I. ; Morris, S.J. ; Custode, F.

Author_Institution

Appl. DSP & VLSI Res. Group, Westminster Univ., London, UK

Volume

5

fYear

2003

Abstract

An ultra-low-power DSP decimation/interpolation structure is described demonstrating how algorithmic and architectural schemes were employed for ultimate power efficiency in a DSP based chip set for audio applications. This circuit was designed and synthesised for a low V_T 0.35 μm CMOS process allowing Nyquist rate signals to be decimated from a high OSR Σ-Δ front-end and interpolation post voice processing at the back end. The DSP has been fabricated and operates down to 0.9 V. At 1.25 V, its current consumption is only 90 μA.

Keywords

CMOS digital integrated circuits; audio signal processing; digital signal processing chips; integrated circuit design; interpolation; logic design; low-power electronics; sigma-delta modulation; speech codecs; 0.35 micron; 0.9 V; 1.25 V; 90 muA; CMOS; DSP engine; Nyquist rate signal decimation; back end interpolation post voice processing; codec DSP; decimation/interpolation structure; high OSR Σ-Δ front-end; power efficiency; ultra-low-power audio applications; CMOS process; Circuit synthesis; Codecs; Digital signal processing; Digital signal processing chips; Engines; Interpolation; Signal design; Signal processing; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206279

Filename

1206279