DocumentCode :
1562209
Title :
High-G drop impact response and failure analysis of a chip packaged printed circuit board
Author :
Jenq, S.T. ; Sheu, H.S. ; Yeh, Chang-Lin ; Lai, Yi-Shao ; Wu, Jenq-Dah
Author_Institution :
Inst. of Aeronaut. & Astronaut., National Cheng Kung Univ., Tainan
Volume :
2
fYear :
2005
Abstract :
This paper is concerned with constructing a high-G drop impact test condition for investigating the impact induced failure phenomenon of the solder ball array located in the chip packaged printed circuit board. An impact environment satisfying the JEDEC B service conditions was constructed using an instrumented drop tower tester. Fifteen wafer-level CSP chips were installed on a standard printed circuit board (PCB) with a dimension of 132 times 77 times 1 mm3. A number of these chip packaged PCB bonded with four different compositions of solder joints with or without lead using the surface mounted technology were studied. During the drop impact tests, the chip packaged PCB circuit was monitored using the multi-event detector system (ETAC) to examine whether circuit fails or not. In addition, the drop impact dynamic response of the PCB and the acceleration at the prescribed location of the drop table were recorded. Transient stress responses in the solder joints were provided using the LS-DYNA explicit code. Numerically predicted failure locations of the solder joints are close to those observed from actual drop impact experiments
Keywords :
ball grid arrays; chip scale packaging; failure analysis; impact testing; printed circuit testing; solders; surface mount technology; JEDEC B service conditions; LS-DYNA explicit code; chip packaged PCB; chip packaged printed circuit board; drop impact dynamic response; drop tower tester; failure analysis; failure locations; high-G drop impact response; high-G drop impact test condition; multievent detector system; solder ball array; solder joints; surface mounted technology; wafer-level CSP chips; Chip scale packaging; Circuit testing; Failure analysis; Instruments; Lead; Poles and towers; Printed circuits; Soldering; Wafer bonding; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th
Conference_Location :
Singapore
Print_ISBN :
0-7803-9578-6
Type :
conf
DOI :
10.1109/EPTC.2005.1614478
Filename :
1614478
Link To Document :
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