Title :
A power efficient register file architecture using master latch sharing
Author :
Wroblewski, Mikolaj ; Mueller, M. ; Wortmann, A. ; Simon, S. ; Pieper, W. ; Nossek, J.A.
Author_Institution :
Munich Univ. of Technol., Germany
Abstract :
This paper introduces a method of reducing area and power consumption of a synthesizable register file by using a single master latch shared by a number of slaves. It investigates potential timing problems and discusses possible solutions. Presented simulation results show that, depending on the size of the register file, reduction of power consumption of more than 50% is achievable.
Keywords :
circuit simulation; digital integrated circuits; flip-flops; integrated circuit layout; logic design; low-power electronics; shift registers; timing; VLSI circuits; area reduction; edge-triggered master-slave D-flip-flops; master latch sharing; power consumption reduction; power efficient register file architecture; semicustom technology; simulation results; single master latch; synthesizable register file; timing problems; Capacitance; Circuit simulation; Clocks; Energy consumption; Flip-flops; Latches; Master-slave; Registers; Tiles; Timing;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206291
