Title :
A 96 × 64 intelligent digital pixel array with extended binary stochastic arithmetic
Author :
Hammadou, Tarik ; Nilson, Magnus ; Bermak, Amine ; Ogunbona, Philip
Author_Institution :
Motorola Labs, Botany, NSW, Australia
Abstract :
A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.
Keywords :
CMOS image sensors; VLSI; digital arithmetic; focal planes; image processing; intelligent sensors; pulse frequency modulation; smart pixels; 0.5 micron; 64 pixel; 96 pixel; CMOS image sensor; binary stochastic arithmetic; chip architecture; focal plane VLSI circuit; intelligent digital pixel array; optical sensor; pixel-level processing; pulse frequency modulator; signal processing; CMOS image sensors; CMOS technology; Digital arithmetic; Optical arrays; Optical pulses; Optical sensors; Pulse modulation; Sensor arrays; Smart pixels; Stochastic processes;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206298
