DocumentCode
1562676
Title
Minimizing coupling jitter by buffer resizing for coupled clock networks
Author
Hsiao, Ming-Fu ; Marek-Sadowska, Malgorzata ; Chen, Sao-Jie
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
5
fYear
2003
Abstract
Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. It is therefore imperative to design clock buffers to reduce the coupling effects. In this paper, we address the crosstalk effect on clock networks. We propose an algorithm to size clock buffers for given buffered clock trees such that the induced clock jitter is minimized. Our experimental results show a significant reduction of clock jitter by sizing the clock buffers without increasing the total area of buffer.
Keywords
VLSI; circuit CAD; clocks; integrated circuit design; timing jitter; buffer resizing; buffered clock trees; chip performance; clock jitter; clock nets; coupled clock networks; coupling effects; coupling jitter; deep submicron technologies; system performance; total area; Capacitance; Clocks; Coupling circuits; Crosstalk; Degradation; Fluctuations; Geometry; Timing jitter; Uncertainty; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206333
Filename
1206333
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