Title :
A resource balancing approach to SoC test scheduling
Author :
Zhao, Dun ; Upadhyaya, S.
Author_Institution :
Dept. of Comput. Sci. & Eng., State Univ. of New York, USA
Abstract :
We present a novel test scheduling algorithm for embedded core-based SoCs. We formulate the test scheduling as a shortest path problem with the feature of evenly balanced resource usage. Improvements to the basic algorithm are sought by core-grouping and all-permutation scheduling. We also extend the algorithm to allow multiple test sets selection to facilitate the testing for various fault models. A simulation study is performed to quantify the benefits of our new scheduling approach.
Keywords :
circuit simulation; integrated circuit testing; logic simulation; logic testing; scheduling; system-on-chip; SoC test scheduling; all-permutation scheduling; core-grouping; embedded core-based SoC; fault models; multiple test sets selection; resource usage balancing; shortest path problem; Built-in self-test; Computer science; Job shop scheduling; Manufacturing processes; Packaging; Process design; Processor scheduling; Scheduling algorithm; Shortest path problem; System testing;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206339
