• DocumentCode
    1562991
  • Title

    Dynamic variable reordering for BDD minimization

  • Author

    Felt, Eric ; York, Gary ; Brayton, Robert ; Sangiovanni-Vincentelli, Alberto

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1993
  • Firstpage
    130
  • Lastpage
    135
  • Abstract
    Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested
  • Keywords
    Boolean functions; computational complexity; formal logic; formal verification; integrated software; logic CAD; logic design; minimisation; BDD minimization; Berkeley; Boolean functions; CPU time; Carnegie Mellon; binary decision diagrams; data structure; dynamic variable reordering; efficient heuristic algorithm; formal verification algorithms; window; Adders; Binary decision diagrams; Boolean functions; Circuits; Data structures; Formal verification; Logic testing; Minimization; Packaging; Problem-solving;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-4350-1
  • Type

    conf

  • DOI
    10.1109/EURDAC.1993.410627
  • Filename
    410627